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Bus Interface Unit (BIU) Registers
23
22
21
20
19
18
17
16
15
14
13
12
BRH
BBS
BDFW4 BDFW3 BDFW2 BDFW1 BDFW0 BA3W2 BA3W1 BA3W0 BA2W2
11
10
9
8
7
6
5
4
3
2
1
0
BA2W1 BA2W0 BA1W4 BA1W3 BA1W2 BA1W1 BA1W0 BA0W4 BA0W3 BA0W2 BA0W1 BA0W0
Reserved bit. Read as zero; write to zero for future compatibility
Figure 4-6. Bus Control Register (BCR)
Table 4-8. Bus Control Register (BCR) Bit Definitions
Bit
Number
23
Bit Name
BRH
Reset Value
0
Bus Request Hold
Description
Asserts the BR signal, even if no external access is needed. When BRH is set, the
BR signal is always asserted. If BRH is cleared, the BR is asserted only if an
external access is attempted or pending.
22
0
Reserved. Write to 0 for future compatibility.
21
BBS
0
Bus State
This read-only bit is set when the DSP is the bus master and is cleared otherwise.
20–16
BDFW[4–0]
11111
(31 wait
states)
Bus Default Area Wait State Control
Defines the number of wait states (one through 31) inserted into each external
access to an area that is not defined by any of the AAR registers. The access type
for this area is SRAM only. These bits should not be programmed as zero since
SRAM memory access requires at least one wait state.
When four through seven wait states are selected, one additional wait state is
inserted at the end of the access. When selecting eight or more wait states, two
additional wait states are inserted at the end of the access. These trailing wait
states increase the data hold time and the memory release time and do not
increase the memory access time.
15–13
BA3W[2–0]
111
Bus Area 3 Wait State Control
(7 wait states) Defines the number of wait states (1–7) inserted in each external SRAM access to
Area 3 (DRAM accesses are not affected by these bits). Area 3 is the area defined
by AAR3.
Note:
Do not program the value of these bits as zero since SRAM memory
access requires at least one wait state.
When four through seven wait states are selected, one additional wait state is
inserted at the end of the access. This trailing wait state increases the data hold
time and the memory release time and does not increase the memory access time.
DSP56311 User’s Manual, Rev. 2
Freescale Semiconductor
4-21
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